The present invention relates to a method for manufacturing an active matrix type liquid crystal display apparatus (TFT-LCD) employing thin film transistors (TFTs) as switching elements. More particularly, the present invention has been made for the sake of preventing corrosion of an storage capacitance wiring group during a successive transparent conductive layer etching process in case a metal material of high corrosiveness is employed for the storage capacitance wiring group or collective drawing wiring.
Electrooptical elements employing liquid crystal are actively being applied for use in displays. Electrooptical elements employing liquid crystal are generally arranged in that liquid crystal is interposed between two upper and lower substrates comprised with electrodes which are further interposed by upper and lower polarizing plates, and in case the electrooptical elements are of transmitting type, a back light is additionally arranged in the rear. So-called alignment is performed for the surfaces of the upper and lower electrode substrates, and directors that are average directions of the liquid crystal molecules can be controlled to provide desired initial conditions. Since liquid crystal presents birefringence, light that has been made incident through the polarizing plate from the back light is changed to elliptical polarization through the birefringence and is made incident to the polarizing plate on the opposite side. In case voltage is impressed between the upper and lower electrodes in this condition, the arranging condition of the directors is changed, resulting in a change in the birefringence rate of the liquid crystal layer, in a change in the condition of elliptic polarization made incident to the polarizing plate on the opposite side, and further in a change in the light intensity and spectrum transmitting through the electrooptical elements. While this electrooptical effect is varied by factors such as the type of liquid crystal layer to be employed, initial orientation condition, direction of the polarizing axis of the polarizing plate, thickness of liquid crystal layer or the color filter or various interference filter that are arranged in the path of the transmitting light, these are reported in details in prior art references. Generally, there are employed arrangements known as TN or STN using nematic liquid crystal layers.
Electrooptical elements for displays using liquid crystal may be divided into simple matrix type ones and TFT-LCDs employing TFTs as switching elements. In view of portability and display quality, TFT-LCDs which present superior characteristics than CRTs or simple matrix type liquid crystal display devices are widely applied to note-type personal computers, for example. A TFT-LCD is generally arranged in that liquid crystal is interposed between a TFT array substrate in which TFTs are formed in a form of an array and an opposing substrate formed with a color filter and with common electrodes, this being further interposed between upper and lower polarizing plates, and a back light is further arranged in the rear. Such an arrangement makes it possible to present favorable color displaying characteristics.
For applying voltage on liquid crystal in a TFT-LCD, the TFTs are switched ON within a selected time for the gate lines, charge is applied to pixel electrodes from a source wiring, and the potential of the pixels are made to be identical with those of the source wiring. In case the gates are in a non-selected condition thereafter, the TFTs are set into an OFF condition. While the charge of the pixels is maintained in this condition, the electric charge of the pixels is actually decreased owing to leakage current of the TFTs or within the liquid crystal so that the potential of the pixels is consequently decreased. In order to prevent such variations in the pixel potential, it is general that an storage capacitance is provided so that the amount of variation in the pixel potential with respect to variations in the unit electric charge is kept small. The storage capacitance may be roughly divided into those arranged by gates and pixel electrodes (additional capacity type) and those arranged by an exclusive wiring and pixel electrodes (storage capacitance wiring type). While an additional capacity type is advantageous in that the aperture ratio can be made large since it is not required for the provision of an exclusive wiring unlike storage capacitance wiring types, the current load becomes large since the gate wiring concurrently serve as an storage capacitance wiring. Since the total sum of wiring resistance and storage capacitance becomes large in a large-sized panel, it is general to employ an storage capacitance wiring for the sake of decreasing the load of the gate wiring. A conceptual diagram of a TFT array substrate employing an storage capacitance wiring is shown in FIG. 10. In the drawing, 1 denotes gate wiring, 8 source wiring, 3 storage capacitance wiring, 10a and 10b collective drawing wiring for impressing voltage on the storage capacitance wiring. On the other hand, it is being attempted to employ wiring materials of low resistance for the sake of decreasing the wiring resistance. In case of employing Al or Al alloys such as AlSiCu or AlCu for the gate wiring in reversed stagger type TFTs and storage capacitance wiring, it may be that hillocks are generated at the time of forming an insulating film on the wiring pattern or that this insulating film is corroded in a succeeding process by the use of strong acid employed at the time of performing pixel pattern etching. In order to eliminate such troubles, it has been attempted in prior art to prevent hillocks by covering the wiring of Al or one of the above noted Al alloys by a metal pattern of high melting point such as Cr or Mo or to prevent hillocks or corrosion through strong acid by performing anodic oxidation of Al or Al alloys. However, the increase in number of photolithographic processes to be performed or the additional step of performing anodic oxidation results in inferior productivity. On the other hand, it has also been attempted to employ Al alloys such as AlZr or AlTa for preventing hillocks, but this resulted in a drawback in that the resistivity was increased to be substantially identical with those of metals of high melting points such as Cr. It has recently been developed of a wiring material as disclosed in Japanese Patent No. 2733006 wherein it is mentioned that with AlNd, hillocks can be prevented without being accompanied by increases in resistivity unlike AlZr as described earlier. It will now been explained for a method of manufacturing a TFT array substrate as shown in FIG. 8 and FIG. 9 which has been manufactured through conventional methods by using AlNd for the gate wiring and storage capacitance wiring.
After forming AlNd onto a glass substrate through spattering to a thickness of 200 nm, wet etching is performed by using a mixed liquid of phosphoric acid, acetic acid and nitric acid to form gate wiring 1, storage capacitance electrodes 2 and storage capacitance wiring 3. At this time, the storage capacitance wiring was connected to a collective drawing wiring 3a on the reverse side of gate terminals. Then, there are successively formed, through plasma CVD, SiN to a thickness of 400 nm as a gate insulating film 4, amorphous Si of 150 nm as a semiconductor layer, and a P doped amorphous Si impurity layer of 30 nm, and a semiconductor pattern 5 is formed on the gate wiring by patterning the impurity layer and semiconductor layer. Thereafter, pixel electrodes 6 are obtained by forming a pixel electrode film to a thickness of 100 nm, which is patterned by a mixed acid of hydrochloric acid and nitric acid or the like. Contact holes 7a are formed through the gate insulating film at an end of the storage capacitance wiring on the side of the gate terminal. After successively forming Cr to a thickness of 400 nm for forming source wiring 8 and drain electrodes 9, patterning is performed. The impurity layer at a channel portion is then removed through dry etching. Finally, SiN is formed to a thickness of 400 nm as a protecting film 11, and SiN at the terminal portion is removed.
In case a film deficit exists in the gate insulating film 4, corrosion and disconnection occurs owing to strong acid employed for performing etching of the pixel electrodes. Recent improvements in film forming devices have enabled to decrease dust whereby large film deficits are hardly generated in gate insulating films. However, in case of minute deficits in gate insulating films or poor coverage of the gate insulating film at the edge step portions of the gate wirings when gate wirings are covered by the gate insulating film, may result in corrosion of the wiring. As explained so far, such problems of disconnection of wiring owing to corrosion need to be considered in case of employing recently developed wiring materials of low resistance and capable of preventing hillocks as common storage capacitance wiring.
Especially, disconnection of common storage capacitance wiring needs to be avoided to the utmost, since the provision of inputting storage capacitance wiring signals from both ends of the wiring makes it impossible to electrically detect disconnection so that pixels of corresponding gate lines present bright line defects at the time the panel is switched ON. As for the storage capacitance wiring and collective drawing wiring pattern, Japanese Patent Application Laid-Open Publication No. 3-72321 (1991) discloses an example wherein an storage capacitance wiring is electrically charged by collective drawing wirings provided at both ends of the panel for improving signal delays of storage capacitance wiring (reference should be made to FIG. 10). However, no reference is made to corrosion of storage capacitance wiring at the time of performing wet etching of a transparent conductive layer which may be problematic in case of employing a metal such as Al for the storage capacitance wiring that is apt to be corroded. Further, Japanese Patent Application Laid-Open Publication No. 7-36061 (1995) discloses an example of a pattern for storage capacitance wiring and collective drawing wiring including patterning of a transparent conductive layer. This reference does also not refer to corrosion of storage capacitance wiring at the time of performing wet etching of a transparent conductive layer which may be problematic in case of employing a corrosive metal such as Al for the storage capacitance wiring.
As described so far, it is an object of the present invention to prevent corrosion and disconnection of storage capacitance wiring generated at the time of performing wet etching of transparent conducive layer in case of employing a corrosive metal such as Al for the storage capacitance wiring.
The electrooptical element according to the present invention as claimed in claim 1 is arranged in that an electrooptical material is interposed between a pair of substrates arranged in an opposing manner wherein one of the substrates comprises thereon a gate wiring, an storage capacitance wiring group formed on a same layer as the gate wiring and formed of one of corrosive metals or of a multi-layered metal including at least one of these metals that underwent corrosion preventing treatments by being separated from each other, a gate insulating layer formed on the substrate so as to cover the gate wiring and the storage capacitance wiring group, TFTs formed on the gate insulating layer, pixel electrodes electrically connected to the TFTs, source wiring intersecting with the gate wiring and provided on the substrate via the gate insulating layer and collective drawing wiring formed on the gate insulating layer for mutually connecting all of each of the storage capacitance wiring group in an electrical manner through contact holes provided on the gate insulating layer.
The electrooptical element according to the present invention as claimed in claim 2 is arranged in that an electrooptical material is interposed between a pair of substrates arranged in an opposing manner wherein one of the substrates comprises thereon a gate wiring, an storage capacitance wiring group and collective drawing wiring formed on a same layer as the gate wiring and formed of one of corrosive metals or of a multi-layered metal including at least one of these metals that underwent corrosion preventing treatments by being separated from each other, a gate insulating layer formed on the substrate so as to cover the gate wiring, the storage capacitance wiring group and the collective drawing wiring, TFTs formed on the gate insulating layer, pixel electrodes electrically connected to the TFTs, source wiring intersecting with the gate wiring and provided on the substrate via the gate insulating layer and a metallic pattern formed on the gate insulating layer for mutually connecting all of each of the storage capacitance wiring group and the collective drawing wiring in an electrical manner through contact holes provided on the gate insulating layer.
The electrooptical element according to the present invention as claimed in claim 3 is characterized in that the storage capacitance wiring group of claim 1 is made of Al, Al alloy or a multi-layered metal including at least one of them.
The electrooptical element according to the present invention as claimed in claim 4 is characterized in that the storage capacitance wiring group and the collective drawing wiring are made of Al, Al alloy or a multi-layered metal including at least one of them.
The electrooptical element according to the present invention as claimed in claim 5 is characterized in that it is arranged in that a pattern is formed between the storage capacitance wiring group and the collective drawing wiring of claim 2 facing to each other in a protruding manner.
The electrooptical element according to the present invention as claimed in claim 6 is arranged in that an electrooptical material is interposed between a pair of substrates arranged in an opposing manner wherein one of the substrates comprises thereon a gate wiring, an storage capacitance wiring group formed on a same layer as the gate wiring and formed of one of corrosive metals or a of multi-layered metal including at least one of these metals that underwent corrosion preventing treatments by being separated from each other, a gate insulating layer formed on the substrate so as to cover the gate wiring and the storage capacitance wiring group, TFTs formed on the gate insulating layer, pixel electrodes electrically connected to the TFTs, source wiring intersecting with the gate wiring and provided on the substrate via the gate insulating layer, a protecting insulating layer formed so as to cover thin film transistors formed on the gate insulating layer and a collective drawing wiring formed on the protecting insulating layer for mutually connecting all of each of the storage capacitance wiring group in an electrical manner through contact holes provided on the gate insulating layer and the protecting insulating layer, wherein the collective drawing wiring is formed of a same material as transfer electrodes formed at a portion that is interposed between the substrate and the opposing substrate for supplying opposing substrate an electrical potential from the substrate to the opposing substrate.
The method for manufacturing electrooptical elements according to the present invention as claimed in claim 7 is characterized in that there are respectively taken the steps of arranging a gate wiring on a substrate, arranging an storage capacitance wiring group formed of one of corrosive metals or of a multi-layered metal film including at least one of these metals that underwent corrosion preventing treatments by being separated from each other, forming a gate insulating layer on the substrate so as to cover the gate wiring and the storage capacitance wiring group, forming a transparent conductive layer on the gate insulating layer, wherein there are further taken the step of forming contact holes on the insulating layer after performing wet etching of the transparent conductive layer, arranging a source wiring which intersects with the gate wiring and is provided on the substrate at least via the gate insulating layer and forming a collective drawing wiring on the substrate for mutually connecting all of each of the storage capacitance wiring group in an electrical manner through the contact holes.
The method for manufacturing electrooptical elements according to the present invention as claimed in claim 8 is characterized in that there are respectively taken the steps of arranging a gate wiring on a substrate, arranging an storage capacitance wiring group and a collective drawing wiring of one of corrosive metals or of a multi-layered metal film including at least one of these metals that underwent corrosion preventing treatments by being separated from each other, forming a gate insulating layer on the substrate so as to cover the gate wiring, the storage capacitance wiring group and the collective drawing wiring, and forming a transparent conductive layer on the gate insulating layer, wherein there are further taken the steps of forming contact holes on the insulating layer after performing wet etching of the transparent conductive layer, arranging a source wiring which intersects with the gate wiring and is provided on the substrate at least via the gate insulating layer and arranging a metal pattern for mutually connecting all of each of the storage capacitance wiring group and the collective drawing wiring in an electrical manner through the contact holes.
The method for manufacturing electrooptical elements according to the present invention as claimed in claim 9 is characterized in that the storage capacitance wiring group of claim 7 is made of Al, Al alloy or a multi-layered metal including at least one of them.
The method for manufacturing electrooptical elements according to the present invention as claimed in claim 10 is characterized in that the storage capacitance wiring group and the collective drawing wiring of claim 8 are made of Al, Al alloy or a multi-layered metal including at least one of them.
The method for manufacturing electrooptical elements according to the present invention as claimed in claim 11 is characterized in that it further includes the steps of arranging patterns that are formed in a protruding manner at one end portion of the storage capacitance wiring group of claim 8, and further arranging protruding patterns at a portion of the collective drawing wiring facing the protruding pattern provided at the storage capacitance wiring group.
The method for manufacturing electrooptical elements according to the present invention as claimed in claim 12 is characterized in that there are respectively taken the steps of arranging a gate wiring on a substrate, arranging an storage capacitance wiring group of corrosive metals or of a multi-layered metal film including at least one of these metals that underwent corrosion preventing treatments by being separated from each other, forming a gate insulating layer on the substrate so as to cover the gate wiring and the storage capacitance wiring group, and forming a transparent conductive layer on the gate insulating layer, wherein there are further taken the steps of forming contact holes on the gate insulating layer after performing wet etching of the transparent conductive layer, and arranging a source wiring which intersects with the gate wiring and is provided on the substrate at least via the gate insulating layer, forming a protecting insulating layer as to cover the source wiring, forming contact holes on the gate insulating layer and the protecting insulating layer, and forming a collective drawing wiring for mutually connecting all of each of the storage capacitance wiring group in an electrical manner through contact holes formed of a same material as transfer electrodes formed at a portion that is interposed between the substrate and the opposing substrate for supplying opposing substrate an electrical potential from the substrate to the opposing substrate.